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VLSI Design

Practical project ideas and implementations for hands-on learning

Delay Estimation

Design Margin - VLSI Design

Device and Circuit Characterization

Device Models - VLSI Design

Interconnect - VLSI Design

Interconnect Simulation

Logical Effort

Power Dissipation - VLSI Design

Reliability - VLSI Design

Scaling - VLSI Design

Spice Tutorial

Transistor Sizing

A Brief History of CMOS Technology

BiCMOS Technology Fabrication

CMOS Layout Design Rules

CMOS Process Enhancements

CMOS Technologies

CV characteristics

DC Transfer Characteristics of CMOS Inverter

Ideal I-V characteristics of MOS Transistor

Manufacturing Issues - CMOS Technology

MOS Transistor

Non ideal I-V effects

Technology Related CAD Issues - CMOS Technology

Boundary Scan

Designs For Testability

Logic Verification

Manufacturing Test

Need For Testing

Silicon Debug Principal

Testers and Test Programs

Text Fixtures

Circuit Design of Latches and Flip Flops

Circuit Families and Its Comparison

Low Power Logic Design

Sequencing Dynamic Circuits

Sequencing Static Circuits

Static Sequencing Element Methodology

Synchronizers - VLSI Design

Circuit Design of Latches and Flip Flops

Circuit Families and Its Comparison

Low Power Logic Design

Sequencing Dynamic Circuits

Sequencing Static Circuits

Static Sequencing Element Methodology

Synchronizers - VLSI Design

Behavioural and RTI Modeling

Data Flow and RTL

Design Hierarchies - VLSI Design

Gate Delays - Verilog HDL

Gate Primitives

Identifiers - Verilog Code

Operators - Verilog HDL

Procedural Assignments Conditional Statements

Specification Using Verilog HDL: Basic Concepts

Structural Gate Level Description of Decoder

Structural Gate Level Switch Level Modeling

Testbenches

Timing Controls - Verilog HDL